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this is information on a product in full production. august 2014 docid13958 rev 9 1/40 a5973ad up to 1.5 a step-down switch ing regulator for automotive applications datasheet - production data features ? qualified following the aec-q100 requirements (see ppap for more details) ? 1.5 a dc output current ? operating input voltage from 4 v to 36 v ? 3.3 v / ( 2%) reference voltage ? output voltage adjustable from 1.235 v to v in ? low dropout op eration: 100% duty cycle ? 500 khz internally fixed frequency ? voltage feed-forward ? zero load current operation ? internal current limiting ? inhibit for zero current consumption ? synchronization ? protection against feedback disconnection ? thermal shutdown applications ? dedicated to automotive applications description the a5973ad is a step-down monolithic power switching regulator with a minimum switch current limit of 1.8 a, so it is able to deliver up to 1.5 a dc current to the load depending on the application conditions. the output voltage can be set from 1.235 v to v in . the high current level is also achieved thanks to an hsop8 package with an exposed frame, that allows to reduce the r th(ja) down to approximately 40 c/w. the device uses an internal p-channel dmos transistor (with a typical r ds(on) of 250 m ? ) as a switching element to minimize the size of the external components. an internal oscillator fixes the switching frequency at 500 khz. having a minimum input voltage of 4 v only it fits the automotive applications requiring the device operation even in cold crank conditions. a pulse- by-pulse current limit with the internal frequency modulation offers an effective constant current short-circuit protection. hsop8 - exposed pad figure 1. application schematic a5973ad www.st.com
contents a5973ad 2/40 docid13958 rev 9 contents 1 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 datasheet parameters over the temperatur e range . . . . . . . . . . . . . . . . 8 5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5.5 error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.6 pwm comparator and power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.7 inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.8 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 additional features and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 zero load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.1 error amplifier and compensation network . . . . . . . . . . . . . . . . . . . . . . . . 16 7.2 lc filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.3 pwm comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
docid13958 rev 9 3/40 a5973ad contents 40 8 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.1 component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.2 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.3 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.4 short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.5 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.6 positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.7 negative buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.8 synchronization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.9 compensation network with mlcc at the output . . . . . . . . . . . . . . . . . . . 33 8.10 external soft_start network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9 typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
pin settings a5973ad 4/40 docid13958 rev 9 1 pin settings 1.1 pin connection figure 2. pin connection (top view) 1.2 pin description table 1. pin description no. pin description 1 out regulator output. 2 synch master/slave synchronization. 3inh a logical signal (active high) disables the device. if inh not used the pin must be grounded. when it is op en an internal pull-up disables the device. 4 comp e/a output for frequency compensation. 5fb feedback input. connecting directly to this pin results in an output voltage of 1.23 v. an external re sistive divider is required for higher output voltages. 6 vref 3.3 v v ref . no cap is requested for stability. 7 gnd ground. 8 vcc unregulated dc input voltage.
docid13958 rev 9 5/40 a5973ad electrical data 40 2 electrical data 2.1 maximum ratings 2.2 thermal data table 2. absolute maximum ratings symbol parameter value unit v 8 input voltage 40 v v 1 out pin dc voltage out pin peak voltage at ? t = 0.1 ? s -1 to 40 -5 to 40 v v i 1 maximum output cu rrent int. limit. v 4 , v 5 analog pins 4 v v 3 inh -0.3 to v cc v v 2 synch -0.3 to 4 v p tot power dissipation at t a ?? 70 c 2 w t j operating junction temperature range -40 to 150 c t stg storage temperature range -55 to 150 c table 3. thermal data symbol parameter value unit r thja maximum thermal resistance junction ambient 40 (1) 1. package mounted on the evaluation board. c/w
electrical characteristics a5973ad 6/40 docid13958 rev 9 3 electrical characteristics t j = -40 c to 125 c, v cc = 12 v, unless otherwise specified. table 4. electrical characteristics symbol parameter test cond ition min. typ. max. unit v cc operating input voltage range 4 36 v r ds(on) mosfet on resistance 0.250 0.5 ? i l maximum limiting current (1) v cc = 5 v 1.8 2.3 a v cc = 5 v, t j = 25 c 2 2.3 f sw switching frequency 425 500 575 khz duty cycle 0 100 % dynamic characteristics v 5 voltage feedback 4.4 v < v cc < 36 v 1.198 1.235 1.272 v h efficiency v 0 = 5 v, v cc = 12 v 90 % dc characteristics i qop total operating quiescent current 57ma i q quiescent current duty cycle = 0; v fb = 1.5 v 2.7 ma i qst-by total standby quiescent current v inh > 2.2 v 50 100 ? a inhibit inh threshold voltage device on 0.8 v device off 2.2 v error amplifier v oh high level output voltage v fb = 1 v 3.5 v v ol low level output voltage v fb = 1.5 v 0.4 v i o source source output current v comp = 1.9 v; v fb = 1 v 190 300 ? a i o sink sink output current v comp = 1.9 v; v fb = 1.5 v 1 1.5 ma i b source bias current 2.5 4 ? a dc open loop gain r l = ? 50 57 db gm transconductance i comp = -0.1 ma to 0.1 ma; v comp = 1.9 v 2.3 ms synch function high input voltage v cc = 4.4 to 36 v 2.5 v ref v low input voltage v cc = 4.4 to 36 v 0.74 v slave synch current (2) v synch = 0.74 v, v synch = 2.33 v 0.11 0.21 0.25 0.45 ma
docid13958 rev 9 7/40 a5973ad electrical characteristics 40 master output amplitude i source = 3 ma 2.75 3 v output pulse width no load, v synch = 1.65 v 0.20 0.35 ? s reference section reference voltage i ref = 0 to 5 ma v cc = 4.4 v to 36 v 3.2 3.3 3.399 v line regulation i ref = 0 ma v cc = 4.4 v to 36 v 510mv load regulation i ref = 0 ma 8 15 mv short-circuit current 5 18 35 ma 1. with t j = 85 c, i lim_min = 2 a, assured by design, characte rization and statistical correlation. 2. guaranteed by design. table 4. electrical characteristics (continued) symbol parameter test cond ition min. typ. max. unit
datasheet parameters over the temperature range a5973ad 8/40 docid13958 rev 9 4 datasheet parameters ov er the temperature range the 100% of the population in the production flow is tested at three different ambient temperatures (-40 ? c; +25 ? c, +125 ? c) to guarantee the datasheet parameters inside the junction temperature range (-40 ? c; +125 ? c). the device operation is so guaranteed when the junction temperature is inside the (-40 ? c; +150 ? c) temperature ra nge. the designer can estimate the silic on temperature increase respect to the ambient temperature evaluating the internal power losses generated during the device operation (please refer to section 2.2 ). however the embedded thermal protection disabl es the switching activity to protect the device in case the junction temperature reaches the t shtdwn (+150 ? c 10 ? c) temperature. all the datasheet parameters can be guarant eed to a maximum junction temperature of +125 ? c to avoid triggering the thermal shutdown protection during the testing phase because of self-heating.
docid13958 rev 9 9/40 a5973ad functional description 40 5 functional description the main internal blocks are shown in the device block diagram in figure 3 . they are: ? a voltage regulator supplying the internal circuitry. from this regulator, a 3.3 v reference voltage is externally available. ? a voltage monitor circuit which checks the input and the internal voltages. ? a fully integrated sawt ooth oscillator with a frequency of 500 khz ?? 15%, including also the voltage feed-forward function and an input/output synchronization pin. ? two embedded current limitation circuits whic h control the current that flows through the power switch. the pulse-by-pulse current limit forces the powe r switch off cycle- by-cycle if the current reaches an internal threshold, while the frequency shifter reduces the switching frequency in order to significantly reduce the duty cycle. ? a transconductance error amplifier. ? a pulse width modulator (pwm) comparator and the relative logic ci rcuitry necessary to drive the internal power. ? a high-side driver for t he internal p-mos switch. ? an inhibit block for standby operation. ? a circuit to implement the thermal protection function. figure 3. block diagram 5.1 power supply an d voltage reference the internal regulator circuit (shown in figure 4 ) consists of a start-up circuit, an internal voltage pre-regulator, the bandgap voltage re ference and the bias block that provides current to all the blocks. the starter supplies the start-up currents to the entire device when the input voltage goes high and the device is enabled (inhibit pin conn ected to ground). the pre-regulator block supplies the bandgap cell with a pre-regulated voltage v reg that has a very low supply voltage noise sensitivity.
functional description a5973ad 10/40 docid13958 rev 9 5.2 voltages monitor an internal block continuously senses the v cc , v ref and v bg . if the voltages go higher than their thresholds, the regulator begins operat ing. there is also a hysteresis on the v cc (uvlo). figure 4. internal circuit 5.3 oscillator and synchronization figure 5 shows the block diagram of the oscillator circuit. the clock generator provides the switching freque ncy of the device, which is internally fixed at 500 khz. the frequency shifter block acts to reduce the switching frequency in case of strong overcurrent or short-circuit. the clock signal is then used in the internal logic circuitry and is the input of the ramp generator and synchronizer blocks. the ramp generator circuit provides the sawt ooth signal, used for pwm control and the internal voltage feed-forward, while the synch ronizer circuit generates the synchronization signal. the device also has a synchronization pi n which can work both as master and slave. beating frequency noise is an issue when more than one voltage rail is on the same board. a simple way to avoid this issue is to operate all the regulators at the same switching frequency. the synchronization feat ure of a set of the a5973ad is si mply get connecting together their synch pin. the device with highest switch ing frequency will be t he master and it provides the synchronization signal to the others. therefore the synch is a i/o pin to deliver or recognize a frequency signal. the synchronization circuitr y is powered by the internal reference (v ref ) so a small filtering capacitor ( ?? 100 nf) connected between v ref pin and the signal ground of the master device is suggested for its proper operation. however when a set of synchronized devices populates a board it is not possible to know in advance the one working as a master, so the filtering capacitor have to be designed for whole set of devices. when one or more devices are synchronized to an external signal, its amplitude have to be in comply with specif ications given in table 4 on page 6 . the frequency of the synchronization signal must be, at a minimum, higher than the maximum guaranteed natural switching frequency of the device (575 khz, see table 4 ) while the duty cycle of the synchronization signal can vary from approximately 10% to 90%. the small capacitor under the v ref pin is required for this operation.
docid13958 rev 9 11/40 a5973ad functional description 40 figure 5. oscillator circuit block diagram figure 6. synchronization example 5.4 current protection the a5973ad device features tw o types of current limit prot ection: pulse-by-pulse and frequency foldback. the schematic of the current limitation circuitry for the pulse-by-pulse protection is shown in figure 7 . the output power pdmos transistor is sp lit into two parallel pdmos transistors. the smallest one includes a resistor in series, r sense . the current is sensed through r sense and if it reaches the threshold, the mi rror becomes unbalanced and the pdmos is switched off until the ne xt falling edge of the inte rnal clock pulse. due to this reduction of the on time, the output voltage decreases. sinc e the minimum switch on time necessary to sense the current in order to avoid a false overcurrent signal is too short to obtain a sufficiently low duty cycle at 500 khz (see section 8.4 on page 26 ), the output current in out gnd comp fb ss/inh a5973d synch out gnd comp fb ss/inh a5973d synch out gnd comp fb ss/inh a5973d synch out gnd comp fb ss/inh a5973d synch out gnd comp fb ss/inh a5973d synch out gnd comp fb ss/inh a5973d synch out gnd comp fb ss/inh a5973d synch out gnd comp fb ss/inh a5973d synch out gnd comp fb ss/inh a5973d synch out gnd comp fb ss/inh a5973d synch out gnd comp fb ss/inh a5973d synch out gnd comp fb ss/inh a5973d synch a5973ad a5973ad a5973ad a5973ad
functional description a5973ad 12/40 docid13958 rev 9 strong overcurrent or short-circuit conditions could be not properly limited. for this reason the switching frequency is also reduced, thus keeping the inductor current under its maximum threshold. t he frequency shifter ( figure 5 ) functions based on the feedback voltage. as the feedback voltage decreases (due to the reduced duty cycle), the switching frequency decr eases also. figure 7. current limitation circuitry 5.5 error amplifier the voltage error amplifier is the core of the loop regulation. it is a transconductance operational amplifier whose no n inverting input is connected to the internal voltage reference (1.235 v), while the inverting input (fb) is connected to the external divider or directly to the output voltage. the out put (comp) is connected to the external compensation network. the uncompensated error amplifier has the following characteristics: the error amplifier out put is compared to the oscillato r sawtooth to perform pwm control. 5.6 pwm comparator and power stage this block compares the oscillator sawtooth and the error amplifie r output signals to generate the pwm signal for the driving stage. the power stage is a highly critical block, as it functions to guarantee a correct turn on and turn off of the pdmos. the turn on of the power element, or more accurately, the rise table 5. uncompensated error amplifier characteristics description values transconductance 2300 s low frequency gain 65 db minimum sink/source voltage 1500 a/300 a output voltage swing 0.4 v/3.65 v input bias current 2.5 a
docid13958 rev 9 13/40 a5973ad functional description 40 time of the current at turn on, is a very critical parameter. at a first approach, it appears that the faster the rise time, the lower the turn on losses. however, there is a limit introduced by the recovery time of the recirculation diode. in fact, when the current of the power element is equal to the inductor current, the diode turns off and the drain of the power is able to go high. but during its recovery time, the diode can be considered a high value capacitor and this produces a very high peak current, responsible for numerous problems: ? spikes on the device supply voltage that ca use oscillations (and thus noise) due to the board parasites. ? turn on overcurrent leads to a decrease in the efficiency and system reliability. ? major emi problems. ? shorter freewheeling diode life. the fall time of the current during turn off is also critical, as it produces voltage spikes (due to the parasites elements of the board) that increase the voltage drop across the pdmos. in order to minimize these problems, a new driving circuit topology has been used and the block diagram is shown in figure 8 . the basic idea is to change the current levels used to turn the power switch on and off, based on the pdmos and the gate clamp status. this circuitry allows the power switch to be turned off and on quickly and addresses the freewheeling diode recovery time problem. the gate clamp is necessary to ensure that v gs of the internal switch does not go higher than v gs max. the on/off control block protects against any cross conduction be tween the supply line and ground. figure 8. driving circuitry
functional description a5973ad 14/40 docid13958 rev 9 5.7 inhibit function the inhibit feature is used to put the device in to standby mode. with the inh pin higher than 2.2 v, the device is disabled and the power consumption is reduced to less than 100 a. with the inh pin lower than 0.8 v, the device is enabled. if the inh pin is left floating, an internal pull up ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. the pin is also v cc compatible. 5.8 thermal shutdown the shutdown block generates a signal that turn s off the power stage if the temperature of the chip goes higher than a fixed internal thre shold (150 10 c). the sensing element of the chip is very close to the pdmos area, ensuring fast and accurate temperature detection. a hysteresis of approximately 20 c keeps the device from turning on and off continuously.
docid13958 rev 9 15/40 a5973ad additional features and protection 40 6 additional features and protection 6.1 feedback disconnection if the feedback is disconnected, the duty cycl e increases towards the maximum allowed value, bringing the output voltage close to the input supply. this condition could destroy the load. to avoid this hazardous condition, the device is turned off if the feedback pin is left floating. 6.2 output overvoltage protection overvoltage protection, or ovp, is achieved by using an internal comparator connected to the feedback, which turns off the power stage when the ovp threshold is reached. this threshold is typically 30% higher than the feedback voltage. when a voltage divider is required to adjust the output voltage ( figure 15 on page 27 ), the ovp intervention will be set at: equation 1 where r 1 is the resistor connected between the output voltage and the feedback pin, and r 2 is between the feedback pin and ground. 6.3 zero load due to the fact that the internal power is a pdmos, no boostrap capacitor is required and so the device works properly even with no load at the output. in this case it works in burst mode, with a random burst repetition rate. v ovp 1.3 r 1 r 2 + r 2 -------------------- ? v fb ? =
closing the loop a5973ad 16/40 docid13958 rev 9 7 closing the loop figure 9. block diagram of the loop 7.1 error amplifier an d compensation network the output l-c filter of a st ep-down converter contributes with 180 degrees phase shift in the control loop. for this reason a compensation network between the comp pin and ground is added. the simplest compensation net work together with the equivalent circuit of the error amplifier are shown in figure 10 . r c and c c introduce a pole and a zero in the open loop gain. cp does not sign ificantly affect system stability but it is useful to reduce the noise of the comp pin. the transfer function of the error amplifier and its compensation network is: equation 2 where a vo = g m r o a 0 s ?? a v0 1s + r c c c ? ? ?? ? s 2 r 0 ? c 0 c p + ?? r c c c sr 0 c c ? r 0 c 0 c p + ?? r c c c ? + ? + ?? 1 + ? + ? ? ? ------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------- =
docid13958 rev 9 17/40 a5973ad closing the loop 40 figure 10. error amplifier equivalent circuit and compensation network the poles of this transfer function are (if c c >> c 0 + c p ): equation 3 equation 4 whereas the zero is defined as: equation 5 f p1 is the low frequency which sets the bandwidth, while the zero f z1 is usually put near to the frequency of the double pole of the l-c filter (see section 7.2 ). f p2 is usually at a very high frequency. f p1 1 2 ? ? r 0 ? c c ? ------------------------------------- = f p2 1 2 ? ? r c ? c 0 c p + ?? ? ------------------------------------------------------- - = f z1 1 2 ? ? r c ? c c ? ------------------------------------- =
closing the loop a5973ad 18/40 docid13958 rev 9 7.2 lc filter the transfer function of the l-c filter is given by: equation 6 where r load is defined as the ratio between v out and i out . if r load >> esr, the previous expression of a lc can be simplified and becomes: equation 7 the zero of this transfer function is given by: equation 8 f 0 is the zero introduced by the esr of the ou tput capacitor and it is very important to increase the phase margin of the loop. the poles of the transfer function can be calculated through the following expression: equation 9 in the denominator of a lc the typical second order system equation can be recognized: equation 10 if the damping coefficient ? is very close to zero, the roots of the equation become a double root whose value is ? n . similarly for a lc the poles can usually be defined as a double pole whose value is: equation 11 a lc s ?? r load 1esrc out s ? ? + ?? ? s 2 lc out esr r load + ?? sesrc out ? r load l + ? ?? r load + ? + ? ? ? ------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------- = a lc s ?? 1 esr c out ? s ? + lc out ? s 2 esr c out ? s1 + ? + ? ---------------------------------------------------------------------------------------------- = f o 1 2 ? ? esr ? c out ? --------------------------------------------------- - = f plc1 2 ? esr c out esr c out ? ?? 2 4l ? c out ? ? ? ? ? 2l ? c out ? ------------------------------------------------------------------------------------------------------------------------------- ----------- = s 2 2 ? ?? n ? s ? 2 n + ? + f plc 1 2 ? ? lc out ? ? ---------------------------------------------- =
docid13958 rev 9 19/40 a5973ad closing the loop 40 7.3 pwm comparator the pwm gain is given by the following formula: equation 12 where v oscmax is the maximum value of a sawtooth waveform and v oscmin is the minimum value. a voltage feed-forward is implemented to ensure a constant gpwm. this is obtained by generating a sawtooth waveform directly proportional to the input voltage v cc . equation 13 where k is equal to 0.038. therefore the pwm gain is also equal to: equation 14 this means that even if the input voltage changes, the error amplifier does not change its value to keep the loop in regulation, thus ensuring a better line regulation and line transient response. in summary, the open loop gain can be expressed as: equation 15 example 1 considering r c = 1.8 k ? , c c = 68 nf and c p = 330 pf, the poles and zeroes of a 0 are: f p1 = 2.9 hz f p2 = 265 khz f z1 = 1.3 khz if l = 12 h, c out = 330 f and esr = 55 m ? , the poles and zeroes of a lc become: f plc = 2.5 khz f zesr = 8.7 khz finally r 1 = 5.6 k ? and r 2 = 3.3 k ? . g pwm s ?? v cc v oscmax v oscmin ? ?? ------------------------------------------------------------- = v oscmax v oscmin ? kv cc ? = g pwm s ?? 1 k --- - const == gs ?? g pwm s ?? r 2 r 1 r 2 + -------------------- ? a o s ?? ? a lc ? s ?? =
closing the loop a5973ad 20/40 docid13958 rev 9 the gain and phase bode diagrams are plotted respectively in figure 11 and figure 12 . figure 11. module plot figure 12. phase plot the cut-off frequency and the phase margin are: equation 16 f c 30khz = phase margin = 66.8
docid13958 rev 9 21/40 a5973ad application information 40 8 application information 8.1 component selection ? input capacitor the input capacitor must be able to support the maximum input operating voltage and the maximum rms input current. since step-down converters draw current from the input in pulses, the input current is squared and the height of each pulse is equal to the output current. the input capacitor has to absorb all this switching curr ent, which can be up to the load current divided by two (worst case, with duty cycle of 50%). for this reason, the quality of these capacitors has to be very high to minimize the power dissipation generat ed by the internal esr, thereby improving system reliability and efficiency. the critical parameter is usually the rms current rating, which must be higher than the rms input current. the maximum rms input current (flowing through the input capacitor) is: equation 17 where ? is the expected system efficiency, d is the duty cycle and i o is the output dc current. this function reaches its maximum valu e at d = 0.5 and the equivalent rms current is equal to i o divided by 2 (considering ? = 1). the maximum and minimum duty cycles are: equation 18 and equation 19 where v f is the freewheeling diode forward voltage and v sw the voltage drop across the internal pdmos. considering the range d min to d max , it is possible to determine the max. i rms going through the input capacitor. capacitors that can be considered are: electrolytic capacitors: these are widely used due to their low pric e and their availabilit y in a wide range of rms current ratings. the only drawback is that, considering ripp le current rating requirements, they are physically larger than other capacitors. ceramic capacitors: if available for the required value and volt age rating, these capacitors usually have a higher rms current rating for a given ph ysical dimension (due to very low esr). the drawback is the considerably high cost. i rms i o d 2d 2 ? ? --------------- - ? d 2 ? 2 ------ - + ? = d max v out v f + v inmin v sw ? ------------------------------------ - = d min v out v f + v inmax v sw ? -------------------------------------- =
application information a5973ad 22/40 docid13958 rev 9 tantalum capacitors: very good, small tantalum capacitors with very low esr are becoming more available. however, they can occa sionally burn if subjected to very high current during charge. therefore, it is better to avoid this type of capacitor for the input filter of the device. they can, however, be subjected to high surge current when connected to the power supply. high dv/dt voltage spikes on the input side can be critical for dc/dc converters. a good power layout and input voltage filtering help to minimize this issue. in addition to the above considerations, a 1 f/50 v ceramic capacitor as close as possible to the vcc and gnd pins is always suggested to adequately filter vcc spikes. ? output capacitor the output capacitor is very important to meet the output voltage ripple requirement. using a small inductor value is useful to reduce the size of the choke but it increases the current ripple. so, to reduce the output voltage ripple, a low esr capacitor is required. nevertheless, the esr of the output capacitor introduces a zero in the open loop gain, which helps to increase the phase margin of the system. if the zero goes to a very high frequency, its effect is neglig ible. for this reason, ceramic capacitors and very low esr capacitors in general should be avoided. tantalum and electrolytic capacitors are usua lly a good choice for this purpose. a list of some tantalum capacitor manufacturers is provided in table 7 . table 6. list of ceramic capacitors for the a5973ad manufacturer series capacitor value ( f) rated voltage (v) taiyo yuden umk325bj106mm-t 10 50 murata grm42-2 x7r 475k 50 4.7 50 table 7. output capacitor selection manufacturer series cap value ( f) rated voltage (v) esr (m ? ) sanyo poscap (1) 1. poscap capacitors have some characterist ics which are very similar to tantalum. tae 100 to 470 4 to 16 25 to 35 thb/c/e 100 to 470 4 to 16 25 to 55 avx tps 100 to 470 4 to 35 50 to 200 kemet t494/5 100 to 470 4 to 20 30 to 200 sprague 595d 220 to 390 4 to 20 160 to 650
docid13958 rev 9 23/40 a5973ad application information 40 ? inductor the inductor value is ve ry important as it fixes the ripple current flowing through the output capacitor. the ripple current is usually fixed at 20 - 40% of i omax , which is 0.3 - 0.6 a with i o max = 1.5 a. the approximate inductor value is obtained using the following formula: equation 20 where t on is the on time of the internal swit ch, given by d t. for example, with v out = 3.3 v, v in = 12 v and ? i o = 0.45 a, the inductor value is about 12 h. the peak current through the inductor is given by: equation 21 and it can be observed that if the inductor va lue decreases, the peak current (which must be lower than the current limit of the device) in creases. so, when the peak current is fixed, a higher inductor value allows a higher value for the output current. in table 8 , some inductor manufacturers are listed. 8.2 layout considerations the layout of switching dc-dc converters is very important to minimize noise and interference. power-generating portions of the layout are the main cause of noise and so high switching current loop areas should be kept as small as possible and lead lengths as short as possible. high impedance paths (in particular the feedback connections) are susceptible to interference, so they should be as far as po ssible from the high current paths. a layout example is provided in figure 13 . the input and output loops are minimized to avoid radiation and high frequency resonance problems. the feedback pin connections to the ex ternal divider are very close to the device to avoid pickup noise. another important issue is the ground plane of the board. since the package has an exposed pad, it is very import ant to connect it to an extended ground plane in order to reduce the thermal resistance junction to ambient. table 8. inductor selection manufacturer series inductor value ( h) saturation current (a) coilcraft do3316t 15 to 33 2.0 to 3.0 coiltronics up1b 22 to 33 2.0 to 2.4 bi hm76-3 15 to 33 2.5 to 3.3 epcos b82476 15 to 33 2 to 3 wurth elektronik 74456115 15 to 33 2.5 to 3 l v in v out ? ?? ? i ---------------------------------- t on ? = i pk i o ? i 2 ----- + =
application information a5973ad 24/40 docid13958 rev 9 figure 13. layout example 8.3 thermal considerations the dissipated power of the device is tied to three different sources: ? conduction losses due to the not insignificant r dson , which are equal to: equation 22 where d is the duty cycle of the application. note th at the duty cycle is theoretically given by the ratio between v out and v in , but in practice it is substant ially higher than this value to compensate for the losses in the overall applic ation. for this reason , the switching losses related to the r dson increases compared to an ideal case. ? switching losses due to turning on and off. these are derived using the following equation: equation 23 where t rise and t fall represent the switching times of the power element that cause the switching losses when driving an inductive load (see figure 14 ). t sw is the equivalent switching time. a5973ad p on r dson i out ?? ? 2 d ? = p sw v in i out t on t off + ?? 2 ----------------------------------- - ? ? f sw v in = ? i out t sw ? f sw ? ? =
docid13958 rev 9 25/40 a5973ad application information 40 figure 14. switching losses ? quiescent current losses. equation 24 where i q is the quiescent current. example 2 ? v in = 12 v ? v out = 3.3 v ? i out = 1.5 a r ds(on) has a typical value of 0.25 at 25 c and increases up to a maxi mum value of 0.5. at 150 c. we can consider a value of 0.4 ? . t sw is approximately 70 ns. i q has a typical value of 2.7 ma at v in = 12 v. the overall losses are: equation 25 the junction temperature of device will be: equation 26 where t a is the ambient temperature and rth j-a is the thermal resistance junction to ambient. considering that the device is mounted on the board with a good ground plane, that it has a thermal resistance junction to ambient (rth j-a ) of about 40 c/w, and an ambient temperature of about 70 c: equation 27 p q v in i q ? = p tot r dson i out ?? ? 2 dv in i out ? t sw ? f sw v in i q = ? + ? + ? = 0.4 1.5 2 ? 0.3 12 1.5 ? 70 ? 10 9 ? ? 500 ? 10 3 12 2.7 ? 10 3 ? ? + ? + ? 0.93w ? = t j t a rth ja ? p tot ? + = t j 70 0.93 42 110 ? c ? ? + =
application information a5973ad 26/40 docid13958 rev 9 8.4 short-circuit protection in overcurrent protection mode, when the peak current reaches the current limit, the device reduces the t on down to its minimum value (approximately 250 nsec) and the switching frequency to approximately one third of its nominal value even when synchronized to an external signal (see section 5.4: current protection on page 11 ). in these conditions, the duty cycle is strongly reduced and, in most app lications, this is enough to limit the current to ilim. in any event, in case of h eavy short-circuit at the output (v o = 0 v) and depending on the application conditions (v cc value and parasitic effect of external components) the current peak could reach values higher than ilim. this can be understood considering the inductor current ripple during the on and off phases: ? on phase equation 28 ? off phase equation 29 where v d is the voltage drop across the diode, dcr l is the series resistance of the inductor. in short-circuit conditions v out is negligible so during t off the voltage across the inductor is very small as equal to the voltage drop across parasitic components (typically the dcr of the inductor and the v fw of the free wheeling diode) while during t on the voltage applied the inductor is instead maximized as approximately equal to v in . so the equation 28 and the equation 29 in overcurrent conditions can be simplified to: equation 30 considering t on that has been already reduced to its minimum. equation 31 considering that f sw has been already reduced to one third of the nominal. in case a short-circuit at the output is applied and v in = 12 v the inductor current is controlled in most of the applications (see figure 15 ). when the application must sustain the short-circuit condition for an extended period , the external components (mainly the inductor and diode) must be selected based on this value. in case the v in is very high, it could occur that the ripple current during t off ( equation 31 ) does not compensate the current increase during t on ( equation 30 ). figure 17 shows an example of a power-up phase with v in = v in max = 36 v where ?? il ton > ? il toff , so the current escalates and the balance between equation 30 and equation 31 occurs at a current slightly higher than the current limit. this must be taken into account in particular to avoid the risk of an abrupt inductor saturation. i l ton ? v in v out ? dcr l r dson + ?? i ? ? l ------------------------------------------------------------------------------------ t on ?? = i l toff ? v d v out dcr l i ? ++ ?? ? l --------------------------------------------------------------- t off ?? = i l ton ? v in dcr l r dson + ?? i ? ? l ---------------------------------------------------------------- t on min ?? v in l -------- - 250ns ?? ? = i l toff ? v d v out dcr l i ? ++ ?? ? l --------------------------------------------------------------- 3t ? sw ?? v d v out dcr l i ? ++ ?? ? l --------------------------------------------------------------- 6 ? s ?? ? =
docid13958 rev 9 27/40 a5973ad application information 40 figure 15. short-circuit current v in = 12 v figure 16. short-circuit current v in = 24 v figure 17. short-circuit current v in = 36 v
application information a5973ad 28/40 docid13958 rev 9 8.5 application circuit figure 18 shows the evaluation board application ci rcuit, where the input supply voltage, v cc , can range from 4 v to 36 v and the output voltage is adjustable from 1.235 v to 6.3 v due to the voltage rating of the output capacitor,. figure 18. evaluation board application circuit table 9. component list reference part number description manufacturer c1 grm42-2 x7r 475k 50 4.7 f, 50 v murata c2 poscap 6tae330ml 330 f, 6.3 v sanyo c3 c1206c221j5gac 47 pf, 5%, 50 v kemet c4 c1206c223k5rac 22 nf, 10%, 50 v kemet r1 5.6 k ? , 1%, 0.1 w 0603 neohm r2 3.3 k ? , 1%, 0.1 w 0603 neohm r3 12 k ? , 1%, 0.1 w 0603 neohm d1 stps3l40u 2 a, 40 v stmicroelectronics l1 do3316t-153mld 15 h, 3.1 a coilcraft a5973ad
docid13958 rev 9 29/40 a5973ad application information 40 figure 19. pcb layout (component side) figure 20. pcb layout (bottom side) figure 21. pcb layout (front side) ls lc
application information a5973ad 30/40 docid13958 rev 9 8.6 positive buck-boost regulator the device can be used to implement a step -up/down converter with a positive output voltage. the output voltage is given by: equation 32 where the ideal duty cycle d for the buck boost converter is: equation 33 however, due to power losses in the passive el ements, the real duty cycle is always higher than this. the real value (that can be measured in the application) should be used in the following formulas. the peak current flowing in the embedded switch is: equation 34 while its average cu rrent is equal to: equation 35 this is due to the fact that th e current flowing through the internal power switch is delivered to the output only during the off phase. the switch peak current must be lower than the minimum current limit of the overcurrent protection (see table 4 on page 6 for details) while the average current must be lower than the rated dc current of the device. as a consequence, the maxi mum output current is: equation 36 where i sw max represents the rated current of the device. the current capability is reduced by the term (1 - d) and so , for example, with a duty cycle of 0.5, and considering an average current through the switch of 1.5 a, the maximum output current deliverable to the load is 0.75 a. v out v in d 1d ? ------------- ? = d v out v in v out + ----------------------------- - = i sw i load 1d ? --------------- i ripple 2 ------------------- - + i load 1d ? --------------- v in 2l ? ---------- - d f sw --------- ? + == i sw i load 1d ? --------------- = i out max i sw max 1d ? ?? ? ?
docid13958 rev 9 31/40 a5973ad application information 40 figure 22 shows the schematic circuit of this topology for a 12 v output voltage and 5 v input. figure 22. positive buck-boost regulator 8.7 negative buck-b oost regulator in figure 23 , the schematic circuit for a standard buck -boost topology is shown. the output voltage is: equation 37 where the ideal duty cycle d for the buck boost converter is: equation 38 the considerations given in section 8.6 for the real duty cycle are still valid here. also the equation 34 till equation 36 can be used to calculate the maximum output current. so, as an example, considering the conversion v in = 12 v to v out = -5 v, i load = 0.4 a: equation 39 equation 40 an important thing to take into account is that the ground pin of the device is connected to the negative output voltage. therefore, the device is subjected to a voltage equal to v in - v o , which must be lower than 36 v (the maximum operating input voltage). a5973ad v out v in ? d 1d ? ------------- ? = d v ? out v in v out ? ----------------------------- - = d 5 512 + --------------- - 0.706 == i sw i load 1d ? --------------- 0.5 10.706 ? ----------------------- - 1.3a == =
application information a5973ad 32/40 docid13958 rev 9 figure 23. negative buck-boost regulator 8.8 synchronization example see section 5.3 on page 10 for details. figure 24. synchronization example a5973ad a5973ad a5973ad
docid13958 rev 9 33/40 a5973ad application information 40 8.9 compensation network with mlcc at the output mlccs (multiple layer ceramic capacitor) with values in the range of 10 f - 22 f and rated voltages in the range of 10 v-25 v are ava ilable today at relatively low cost from many manufacturers. these capacitors have very low esr values (a few m ? ) and thus are occasionally used for the output filter in order to reduce the voltage ripple and the overall size of the application. however, a very low esr value affects the compensation of the loop (see section 7 on page 16 ) and in order to keep the system stable, a more complicated compensation network may be required. however, due to the architecture of the internal error amplifier the bandwidth with this compensa tion is limited. that is why output capacitors with a not negligible esr are suggested. the selection of the output capacitor have to guarantee that the zero introduced by this co mponent is inside the designed system bandwidth and close to the fr equency of the double pole introduced by the lc filter. a general rule for th e selection of this compound for the system stability is provided in equation 41 . equation 41 figure 25 shows an example of a compensation net work stabilizing the system with ceramic capacitors at the output (the optimum co mponent value depends on the application). figure 25. mlcc compensation network example f z esr 1 2 ? esr c out ?? ? ----------------------------------------------- - = bandwidth ? f lc f ? z esr 10 f lc ? ? a5973ad
application information a5973ad 34/40 docid13958 rev 9 8.10 external soft_start network at the start-up the device can quickly increase the current up to the current limit in order to charge the output capacitor. if soft ramp up of the output voltage is required, an external soft-start network can be implemented as shown in figure 26 . the capacitor c is charged up to an external reference through r and the bjt clamps the comp pin. this clamps the duty cycle, limiting the slew rate of the output voltage. figure 26. soft-start network example a5973ad
docid13958 rev 9 35/40 a5973ad typical characteristics 40 9 typical characteristics figure 27. junction temperature vs. output current - v in = 5 v figure 28. junction temperature vs. output current - v in = 12 v figure 29. load regulation figure 30. line regulation figure 31. output voltage vs. junction temperature figure 32. shutdown current vs. junction temperature 3.276 3.28 3.284 3.288 3.292 3.296 3.3 3.304 3.308 3.312 00.511.5 io (a) vo (v) tj = 125c tj = 25c vcc = 12v vo = 3.3v 3.276 3.28 3.284 3.288 3.292 3.296 3.3 3.304 3.308 3.312 0102030 4 0 vcc (v) tj = 125c tj = 25c vcc = 12v vo = 3.3v vo (v) tj (c) vcc=12v 1.2 1.21 1.22 1.23 1.24 1.25 -50 0 50 100 150 vo (v) vcc = 12v 30 40 50 60 70 -50 0 50 100 150 ishd ( ? a) vcc = 12v tj (c)
typical characteristics a5973ad 36/40 docid13958 rev 9 figure 33. efficiency vs. output current - v in = 12 v figure 34. efficiency vs. output current - v in = 5 v
docid13958 rev 9 37/40 a5973ad package information 40 10 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at: www.st.com . ecopack is an st trademark. figure 35. hsop8 package outline
package information a5973ad 38/40 docid13958 rev 9 table 10. hsop8 package mechanical data symbol dimensions mm inch min. typ. max. min. typ. max. a 1.70 0.0669 a1 0.00 0.10 0.00 0.0039 a2 1.25 0.0492 b 0.31 0.51 0.0122 0.0201 c 0.17 0.25 0.0067 0.0098 d 4.80 4.90 5.00 0.1890 0.1929 0.1969 d1 3 3.1 3.2 0.118 0.122 0.126 e 5.80 6.00 6.20 0.2283 0.2441 e1 3.80 3.90 4.00 0.1496 0.1575 e2 2.31 2.41 2.51 0.091 0.095 0.099 e1.27 h 0.25 0.50 0.0098 0.0197 l 0.40 1.27 0.0157 0.0500 k0 (min.), 8 (max.) ccc 0.10 0.0039
docid13958 rev 9 39/40 a5973ad ordering information 40 11 ordering information 12 revision history table 11. ordering information order code package packaging a5973ad hsop8 tube A5973ADTR tape and reel table 12. document revision history date revision changes 07-aug-2007 1 initial release 31-oct-2007 2 updated: table 4 on page 6, table 5 on page 12 14-jan-2008 3 updated table 5 on page 12 02-may-2008 4 updated table 4 on page 6 27-aug-2008 5 updated table 4 on page 6 22-apr-2009 6 updated chapter 7 on page 16 04-nov-2009 7 updated figure 29 , figure 30 , figure 31 , figure 32 on page 35 and table 4 on page 6 27-may-2014 8 updated section 8.1: component selection on page 21 (added text below table 6 ). updated titles of figure 27 on page 35 , figure 28 on page 35 , figure 33 on page 36 , and figure 34 on page 36 (added v in values). updated section 10: package information on page 37 (updated titles, reversed order of figure 35 and table 10 , updated header of table 10 ). added section 11: ordering information . updated cross-references throughout document minor modifications throughout document. 12-aug-2014 9 updated unit in table 4 on page 6 (replaced ?w? by ? ? ? in row of r ds(on) symbol).
a5973ad 40/40 docid13958 rev 9 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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